1. Field of the Invention
The present invention relates generally to the design of integrated circuits. More specifically, but without limitation thereto, the present invention relates to methods of generating a layout for a hierarchical integrated circuit design.
2. Description of Related Art
Typically, a layout, or physical design, for an integrated circuit is generated from a schematic. A schematic defines the logical functions performed by the integrated circuit and how the functions are interconnected. The layout, or floorplan, defines the physical components used to construct the functions defined in the schematic. For economy of design, a schematic for an integrated circuit design typically contains basic functions that are combined to form function blocks that are combined to form more complex function blocks, and so on. This type of schematic is referred to as a hierarchical schematic. In previous methods for generating a layout for the integrated circuit, the hierarchical schematic is flattened or expanded to generate a layout for every instance of every function block in the integrated circuit design.